Patent attributes
A system is disclosed. The system includes a first stage configured to receive VIN and VREF, the first stage including an input transistor pair, wherein the input voltage is coupled to the input transistor pair, the input transistor pair is coupled to ground, and the input transistor pair includes at a common drain a high-gain node having a voltage VHGN. The system further include a second stage coupled to the high-gain node and configured to generate VOUT based on a difference between VIN and VREF, the second stage comprising a resistor and an inverter transistor pair, wherein the gates of the inverter transistor pair are coupled to the high-gain node of the first stage and the resistor couples the high-gain node of first stage to a common drain of the inverter transistor pair and is configured to provide and/or draw current to and/or from the high-gain node of first stage.
