Patent attributes
A bus arrangement includes a coordinator that has a non-volatile memory; a first node that has a first serial number; a second node that has a second serial number; and a bus. The bus includes a first signal line, which couples the first node and the coordinator; a second signal line, which connects the second node to the first node; and at least one bus line, which connects the coordinator to the first and the second nodes. The coordinator is configured such that, in a configuration phase, it establishes a connection to the first node, queries the first serial number, and stores the first serial number in the non-volatile memory, and establishes a connection to the second node, queries the second serial number, and stores the second serial number in the non-volatile memory.
