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US Patent 10467059 Determination of timing configurations for program dataflow models

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Contents

Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
104670590
Patent Inventor Names
Rhishikesh Limaye0
Trung N. Tran0
Ankita Prasad0
Arkadeb Ghosal0
Hugo A. Andrade0
Jacob Kornerup0
Kaushik Ravindran0
Patricia Derler0
Date of Patent
November 5, 2019
0
Patent Application Number
154717920
Date Filed
March 28, 2017
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Patent Citations
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US Patent 10114917 Systems and methods for mapping executable models to programmable logic device resources
Patent Citations Received
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US Patent 12001321 Automated mocking of computer system deployments
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US Patent 11520675 Accelerated replay of computer system configuration sequences
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US Patent 11663112 Selection of computer system deployments to mock for testing
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US Patent 11467947 Automated mocking of computer system deployments
Patent Primary Examiner
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Christopher B. Shin
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Patent abstract

A method for determining timing constraints in dataflow models is disclosed. The method includes receiving node information specifying a plurality of dataflow nodes, as well as coupling between various ones of the dataflow nodes. The method further comprising receiving timing information specifying timing constraints for at least some of the dataflow nodes. Based on the node information, the couplings between the nodes, and the timing information, a timeline dependency graph (TDG). The timeline dependency graph illustrates a timeline, mappings between nodes with side effects to firing times of those nodes on the timeline, and dependencies between nodes.

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