Patent attributes
A device includes a memory-cell array and a sense-amplifier. A decoder connects a first BL to the sense amplifier. The decoder includes first and second multiplexers. The first multiplexer includes a first n-type transistor and a first p-type transistor. The first n-type transistor is connected to the first BL and capable of applying a first voltage for writing a first logic or a non-select voltage for not writing data to the first BL. The first p-type transistor is connected to the first BL and capable of applying a second voltage for writing a second logic or the non-select voltage to the first BL. The second multiplexer is connected between the first multiplexer and the sense amplifier and transmits the first voltage or the non-select voltage to the first n-type transistor and transmits the second voltage or the non-select voltage to the first p-type transistor.
