US Patent 10475752 Semiconductor package structure and method of making the same

A semiconductor package structure includes a substrate, a chip, bumps, an encapsulation layer and a thermal expansion-matching layer. The chip is located on a top surface of the substrate. The bumps electrically connect the chip and the inner connection pads of the substrate. The encapsulation layer covers the bumps, the chip and the top surface of the substrate. The thermal expansion-matching layer covers the whole top surface of the encapsulation layer, and exposes the side surfaces of the encapsulation layer. The thermal expansion coefficient of the thermal expansion-matching layer is different from that of the encapsulation layer. The side surface of the thermal expansion-matching layer is flush with that of the encapsulation layer. The thermal expansion-matching layer balances the inner stresses caused by the difference of the thermal expansion. Thus, the invention reduces the warpage problem of the formed package.