US Patent 10497437 Decoding scheme for 3D cross-point memory array

An integrated circuit includes a three-dimensional cross point memory array having M levels of memory cells disposed in cross points of N first access line layers and P second access line layers. The integrated circuit further comprises first and second sets of first access line drivers. The first set of first access line drivers is operatively coupled to apply a common first operational voltage to selected first access lines in odd first access line layers. The second set of first access line drivers is operatively coupled to apply the common first operational voltage to selected first access lines in even first access layers. A plurality of sets of second access line drivers is operatively configured to apply a second operational voltage to selected second access lines in selected second access line layers.