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US Patent 10504577 Apparatus with a row hit rate/refresh management mechanism

Patent 10504577 was granted and assigned to Micron Technology on December, 2019 by the United States Patent and Trademark Office.

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Patent Citations Received
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US Patent 12125514 Apparatuses and methods for access based refresh operations
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US Patent 12112787 Apparatuses and methods for access based targeted refresh operations
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US Patent 12002501 Apparatuses and methods for distributed targeted refresh operations
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US Patent 11955158 Apparatuses and methods for access based refresh timing
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US Patent 11935576 Semiconductor device performing row hammer refresh operation
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US Patent 11869567 Refresh control circuit and memory
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Patent abstract

The apparatus includes: a row hammer refresh (RHR) circuit configured to: steal a first stolen cycle to implement an RHR operation or a portion thereof, and steal a second stolen cycle after one or more operating cycles, the second stolen cycle to implement the RHR operation or a different portion thereof.

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US Patent 11749331 Refresh modes for performing various refresh operation types
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US Patent 11715512 Apparatuses and methods for dynamic targeted refresh steals
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US Patent 11651810 Memory system and memory module including memory chips sharing channel
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US Patent 11610622 Apparatuses and methods for staggered timing of skipped refresh operations
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Infobox
Is a
Patent
Patent
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Patent Applicant
Micron Technology
Micron Technology
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Current Assignee
Micron Technology
Micron Technology
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
105045770
Date of Patent
December 10, 2019
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Patent Application Number
161811170
Date Filed
November 5, 2018
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Patent Citations
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US Patent 10157658 Refresh control device
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Patent Citations Received
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US Patent 11238916 Method for refreshing a memory device, in which the victim row refresh operation is hidden in the normal refresh operation without affecting the time allocated for the normal refresh operation
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US Patent 10937468 Memory with configurable die powerup delay
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US Patent 10991413 Memory with programmable die refresh stagger
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US Patent 11250890 Memory with configurable die powerup delay
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US Patent 11264079 Apparatuses and methods for row hammer based cache lockdown
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US Patent 11270750 Semiconductor device performing row hammer refresh operation
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US Patent 11302374 Apparatuses and methods for dynamic refresh allocation
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US Patent 11302377 Apparatuses and methods for dynamic targeted refresh steals
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US Patent 11309010 Apparatuses, systems, and methods for memory directed access pause
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US Patent 11309012 Apparatuses and methods for staggered timing of targeted refresh operations
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US Patent 11315619 Apparatuses and methods for distributing row hammer refresh events across a memory device
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US Patent 11315620 Semiconductor device performing row hammer refresh operation
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US Patent 11348631 Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed
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US Patent 11380382 Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit
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US Patent 11417383 Apparatuses and methods for dynamic refresh allocation
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US Patent 11482271 Memory with programmable die refresh stagger
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US Patent 11508429 Memory system performing hammer refresh operation and method of controlling refresh of memory device
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US Patent 11532346 Apparatuses and methods for access based refresh timing
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US Patent 11557331 Apparatuses and methods for controlling refresh operations
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Patent Primary Examiner
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Xiaochun L Chen
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