US Patent 10504959 Semiconductor memory device

A lower dielectric layer is disposed on a semiconductor substrate. A plurality of peripheral lower wirings are disposed on a peripheral region of the semiconductor substrate and in the lower dielectric layer. An upper dielectric layer is disposed on the lower dielectric layer and covers the plurality of peripheral lower wirings. A mold layer is disposed on the upper dielectric layer and includes an etching stopper layer. A peripheral upper wiring penetrates the mold layer and the upper dielectric layer to be connected to at least one of the plurality of peripheral lower wirings. The peripheral upper wiring includes a wiring portion, a first via portion extending downwardly from a bottom surface of the wiring portion, and a second via portion extending downwardly from the bottom surface of the wiring portion.