Patent attributes
A method includes forming a stack of semiconductor material layers. A first spacer is formed adjacent a lower region at a first end of the stack, and a second spacer is formed adjacent an upper region positioned at a second end of the stack. A gate structure and sidewall spacer are formed above the stack. The gate structure and a first subset of the semiconductor layers are removed to define inner cavities and a gate cavity. A gate insulation layer is formed. A first conductive material is formed in the inner cavities. The first conductive material is selectively removed from the inner cavities in the upper region. The first conductive material in the inner cavities in the lower region remains as a first gate electrode. A second conductive material is formed in the inner cavities in the upper region to define a second gate electrode.
