US Patent 10515444 Care area generation for inspecting integrated circuits

Methods and systems for inspecting integrated circuits are provided. The method includes generating care areas that each includes at least one potential defect, organizing the generated care areas based on a first set of spatial relationships to provide a list of neighboring care areas, wherein each neighboring care area is an entry within the list, and generating a recipe file of the list, wherein each neighboring care area is inspected sequentially using a high-resolution inspection system. The system comprises a memory including instructions executable by a processor to: generate care areas that each includes at least one potential defect, organize the generated care areas based on a first set of spatial relationships to provide a list of neighboring care areas that are each an entry within the list, and generate a recipe file of the list, wherein each neighboring care area is inspected sequentially using a high-resolution inspection system.