US Patent 10515692 Programming memories with stepped programming pulses

Methods of operating a memory device applying a programming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a particular memory cell of the plurality of memory cells for programming while the programming pulse has a particular voltage level of the plurality of different voltage levels, and, after enabling the particular memory cell for programming, inhibiting the particular memory cell from programming while the programming pulse has a second voltage level of the plurality of different voltage levels, different than the particular voltage level.