US Patent 10522462 Memory array structure having multiple bit lines
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Patent abstract
Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.
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Patent Inventor Names
Jhon Jhy Liaw0
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Patent Jurisdiction
Patent Number
105224620
Date of Patent
December 31, 2019
0Patent Application Number
160482620
Date Filed
July 28, 2018
0Patent Primary Examiner
Edits on 31 Jan, 2022
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US Patent 10522462 Memory array structure having multiple bit lines
Infobox
Is a
Patent jurisdiction
Patent number
10522462
Date of patent
December 31, 2019
Patent application number
16048262
Date Filed
July 28, 2018
Patent primary examiner
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