US Patent 10522488 Patterning polymer layer to reduce stress
Patent 10522488 was granted and assigned to Taiwan Semiconductor Manufacturing Company on December, 2019 by the United States Patent and Trademark Office.
All edits
A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.
US Patent 10522488 Patterning polymer layer to reduce stress
Find more entities like US Patent 10522488 Patterning polymer layer to reduce stress
