US Patent 10528414 Centralized error handling in application specific integrated circuits

In one embodiment, a system comprises a plurality of hardware blocks, each of the plurality of hardware blocks configured to perform a function in response to a request associated with a command, an error queue manager configured to receive an error message from at least one of the plurality of hardware blocks and store the error message in an error queue, the error message including a command identifier of a command in error, and an error state manager including an error state bitmap, the error state bitmap storing an error state bit for each of a plurality of command identifiers, the error state bit indicating either command in error or command not in error; the error state manager configured to set the error state bit for the command identifier of the command in error to indicate command in error in response to an error state message, the error state message including the command identifier of the command in error.