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US Patent 10534616 Load-hit-load detection in an out-of-order processor
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Patent
Date Filed
October 6, 2017
Date of Patent
January 14, 2020
Patent Application Number
15726563
Patent Citations Received
US Patent 11914998 Processor circuit and data processing method for load instruction execution
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US Patent 10942743 Splitting load hit store table for out-of-order processor
US Patent 10963248 Handling effective address synonyms in a load-store unit that operates without address translation
US Patent 11593109 Sharing instruction cache lines between multiple threads
US Patent 11593108 Sharing instruction cache footprint between multiple threads
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US Patent 11687337 Processor overriding of a false load-hit-store detection
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US Patent 11748267 Concurrent processing of translation entry invalidation requests in a processor core
US Patent 10725783 Splitting load hit store table for out-of-order processor
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Patent Inventor Names
Bryan Lloyd
0
Christopher Gonzalez
0
Balaram Sinharoy
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10534616
Patent Primary Examiner
Daniel H Pan
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