US Patent 10534878 Circuit place and route optimization based on path-based timing analysis

A graph-based analysis (GBA) output is obtained comprising timing information pertaining to a plurality of paths in an integrated circuit. A path-based analysis (PBA) is performed on the GBA output to analyze timing of the plurality of paths and generate a set of improved timing results; wherein the physical measurements used by the PBA are more accurate than the physical measurements used by the GBA. The PBA result is output to an optimizer to automatically adjust the circuit.