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US Patent 10535631 3D Chip-on-wager-on-substrate structure with via last process
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Patent
Date Filed
December 17, 2018
Date of Patent
January 14, 2020
Patent Applicant
Taiwan Semiconductor Manufacturing Company
Patent Application Number
16221831
Patent Citations
US Patent 10163859 Structure and formation method for chip package
Patent Citations Received
US Patent 11791242 Semiconductor device
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10535631
Patent Primary Examiner
Telly D Green
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