US Patent 10535667 Memory array and semiconductor chip

A memory array and a semiconductor chip are provided. The memory array includes memory cells, each includes: first and second pull-up transistors, first and second pull-down transistors, and first and second pass-gate transistors. A source/drain of the first pull-up transistor is coupled to a source/drain of the first pull-down transistor. A source/drain of the second pull-up transistor is coupled to a source/drain of the second pull-down transistor. Gates of the second pull-up and pull-down transistors are coupled to the first node. Gates of the first pull-up and pull-down transistors are coupled to the second node. The first and second pass-gate transistors are respectively coupled to the first and second nodes. The first and second pull-up transistors respectively include a first active structure having a bottom portion including a strained semiconductor material and a top portion including an unstrained semiconductor material. The first active structures continuously extend across the memory array.