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US Patent 10536258 Skew compensation for multi-domain clock generation

Patent 10536258 was granted and assigned to Texas Instruments on January, 2020 by the United States Patent and Trademark Office.

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Patent
Patent
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Patent attributes

Patent Applicant
Texas Instruments
Texas Instruments
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Current Assignee
Texas Instruments
Texas Instruments
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
105362580
Patent Inventor Names
Charles Kasimer Sestok0
Nikolaus Klemmer0
Srinadh Madhavapeddi0
Vijayavardhan Baireddy0
Hamid Safiri0
Hunsoo Choo0
Jaimin Mehta0
Date of Patent
January 14, 2020
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Patent Application Number
159964440
Date Filed
June 2, 2018
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Patent Citations Received
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US Patent 12021960 Maintaining a virtual time of day
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US Patent 11502764 FSYNC mismatch tracking
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US Patent 11502812 Data protocol over clock line
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US Patent 11526193 Maintaining the correct time when counter values are transferred between clock domains
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US Patent 11061432 Data handoff between two clock domains sharing a fundamental beat
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US Patent 11290250 Phase transport with frequency translation without a PLL
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US Patent 11296806 Shared communication channel that interleaves 1 PPS signals and messaging
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US Patent 11664968 Secondary phase compensation assist for PLL IO delay aligning sync signal to system clock signal
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Patent Primary Examiner
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Khai Tran
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Patent abstract

Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.

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