US Patent 10541242 Vertical transistor with eDRAM

Structures and methods for making vertical transistors in the Embedded Dynamic Random Access Memory (eDRAM) scheme are provided. A method includes: providing an SOI substrate with a buried insulator layer therein, forming a trench through the substrate, filling the trench with a first polysilicon material, and after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a doped layer over the SOI substrate, wherein the grown second polysilicon material and epitaxially grown doped layer form a basis for a strap merging the doped layer and the second polysilicon material.