US Patent 10545822 Semiconductor device

An address processing circuit may be provided. The address processing circuit may include an address latch control circuit configured to generate a plurality of latch control signals for separately inputting/outputting a normal operation-related address signal or a data error correction operation-related address signal based on a plurality of internal command signals pertaining to a normal operation and an error correction operation. The address processing circuit may include an address latch circuit configured to latch a combined address signal for the normal operation and the error correction operation to a pipe latch according to any one of the plurality of latch control signals, and separately output the latched combined address signal for the normal operation or the data error correction operation according to the other signals of the plurality of latch control signals.