Patent attributes
An integrated circuit including a first multiplexor configured to receive one of a plurality of diagnostic signals from circuitry under test (DUT), the first multiplexor responsive to diagnostic signals provided thereto and configured to selectively output one of the diagnostic signals in response to a control signal, a second multiplexor configured to receive one of a plurality of reference signals from one of a plurality of nodes on a reference circuit, the second multiplexor configured to selectively output one of the diagnostic signals in response to a control signal, and a comparator configured to compare the diagnostic signal elicited from the first multiplexor with the reference signal elicited from the second multiplexor, the comparator further configured to output the result of the comparison between the diagnostic signal and the reference signal.
