US Patent 10559493 Multifunction single via patterning

A method for semiconductor device fabrication includes forming storage elements on conductive structures. A cap layer is deposited over the storage elements and the conductive structures. An interlevel dielectric (ILD) layer is formed over the cap layer. Trenches are patterned in the ILD layer to expose a top portion of the storage elements. The storage elements where interlevel vias are to be formed is removed to expose the conductive structures therebelow to form via openings. A conductive material is deposited in the trenches and the via openings to concurrently make contact with the storage elements and form interlevel vias in the via openings.