US Patent 10564972 Apparatus and method for efficiently reclaiming demoted cache lines

An apparatus and method for efficiently reclaiming demoted cache lines. For example, one embodiment of a processor comprises: a cache hierarchy including at least one Level 1 (L1) cache and one or more lower level caches; a decoder to decode a cache line (CL) demote instruction specifying at least a first cache line; and execution circuitry to demote the first cache line responsive to the CL demote instruction, the execution circuitry to implement a writeback operation on the first cache line if the first cache line has been modified and homed in a specified memory tier or a default memory tier specified in a register.