US Patent 10566051 Semiconductor memory device and memory system

According to one embodiment, a semiconductor memory device includes a first memory cell capable of storing 3-bit data. When first data including a first bit and a second bit is received from an external controller, the received first data is written to the first memory cell. When second data including a third bit and a fourth bit is received after the first data is received from the controller, the first data is read from the first memory cell and the 3-bit data is written to the first memory cell based on 1-bit of the read first data and the received second data.