Patent attributes
A bi-directional level translator with fast rise and fall times and low current leakage is suitable for use with devices connected using a SPMI bus. The level translator passes signals between first and second voltage domains that operate at different voltage levels. The level translator has a first terminal that receives a first signal A from the first voltage domain and outputs a second signal B to the second voltage domain. A second terminal receives the second signal B and outputs the first signal A. A first switch is located between the first voltage source and the first terminal and a second switch is located between the second voltage source and the second terminal. The first and second switches are operable to reduce current leakage of the level translator.
