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US Patent 10572409 Sparse matrix processing circuitry

Patent 10572409 was granted and assigned to Xilinx on February, 2020 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
Current Assignee
Xilinx
Xilinx
Date Filed
May 10, 2018
Date of Patent
February 25, 2020
Patent Applicant
Xilinx
Xilinx
Patent Application Number
15976722
Patent Citations Received
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US Patent 12124383 Systems and methods for cache optimization
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US Patent 12079155 Graphics processor operation scheduling for deterministic latency
0
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US Patent 12079484 Random reads using multi-port memory and on-chip memory blocks
0
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US Patent 12093210 Compression techniques
0
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US Patent 10936311 Sparse matrix processing circuitry
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US Patent 11379707 Neural network instruction set architecture
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US Patent 11422801 Neural network compute tile
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US Patent 11842423 Dot product operations on sparse matrix elements
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US Patent 11934342 Assistance for hardware prefetch in cache access
0
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US Patent 11954062 Dynamic memory reconfiguration
0
•••
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10572409
Patent Primary Examiner
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Chun Kuan Lee

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