US Patent 10572619 Pseudo-asynchronous digital circuit design

A logic element includes a logic block, a clock generator, a clock assigner and at least one sampling element. The logic block implements a logic function on input data to obtain a plurality output data signals. The output data signals are sampled by respective clock signals. The clock generator generates phase-shifted clock signals from a reference clock signal. The clock assigner assigns differing ones of the phase-shifted clock signals to respective output data signals. The sampling element(s) sample the output data signals in accordance with the respective assigned phase-shifted clock signals.