US Patent 10573638 ESD protection circuit assembly for CMOS manufacturing process

An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.