Patent attributes
A method of forming a device that includes encapsulating a magnetic resistive access memory (MRAM) stack with a first patternable low-k dielectric material that is patterned by a exposure to produce a via pattern that extends to circuitry to logic devices. The via pattern is developed forming a via opening. The method further includes forming a second patternable low-k dielectric material over first patternable low-k dielectric material and filling the via opening. The second patternable low-k dielectric material is patterned by a light exposure to produce a first line pattern to the MRAM stack and a second line pattern to the via opening. The first line pattern and the second line pattern are developed to form trench openings. Thereafter, electrically conductive material is formed in the trench openings and the via opening.