US Patent 10580501 Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a memory cell array having a plurality of memory cells, a plurality of bit lines, each bit line being connected to one of the memory cells in the plurality of memory cells, and a word line commonly connected to the plurality of memory cells. A control circuit is configured to apply a program voltage to the word line and to change a voltage applied to a first bit line in the plurality of bit lines within a first period in which the program voltage is being applied to the word line.