US Patent 10580900 Nanosheet channel post replacement gate process

Device and method for fabricating a field effect transistor (FET) include forming plurality of dummy dielectric layers separated by a corresponding plurality of source/drain regions overlying a substrate. One or more nanosheets of active transistor channels alternating between the plurality of dummy dielectric layers are formed extending at least part way into the plurality of source/drain regions. A high-k dielectric layer is formed about and overlying the source/drain regions and portions of the one or more nanosheets not covered by the plurality of dummy dielectric layers. A conductive metal cap layer is formed overlying the high-k dielectric layer.