Patent attributes
Semiconductor-on-insulator field effect transistor (FET) integrated circuit (IC) structures and fabrication processes that mitigate or eliminate the problems caused by the secondary parasitic back-channel FET of conventional semiconductor-on-insulator FET IC structures. Embodiments enable full control of the secondary parasitic back-channel FET of semiconductor-on-insulator IC primary FETs. Embodiments include taking partially fabricated ICs made using a process which allows access to the back side of the FET, such as “single layer transfer” process, and then fabricating a conductive aligned supplemental (CAS) gate structure relative to the insulating layer juxtaposed to a primary FET such that a control voltage applied to the CAS gate can regulate the electrical characteristics of the regions of the primary FET adjacent the insulating layer. The IC structures present as a four or five terminal device: source S, drain D, primary gate G, CAS gate, and, optionally, a body contact.
