Patent attributes
A bi-directional ESD protection device for an RF circuit that utilizes two pre-driver FETs to reliably maintain the gate voltage of a ggNMOS-type main transistor the lowest applied voltage (e.g., 0V) in order to maximize the main transistor's drain-to-source breakdown voltage, which determines the trigger voltage of the ESD protection device. One pre-driver FET couples the main transistor's gate to ground during positive voltage input signal phases, and the other pre-driver FET couples the main transistor's gate to the input signal path during negative voltage input signal phases. While the amplitude of the input signals remains below the main transistor's trigger voltage, the main transistor remains completely turned off, whereby the input signals are passed to I/O circuitry with minimal interference. Whenever the input signal exceeds the trigger voltage, the main transistor turns on to shunt the over-voltage/current to ground, thereby protecting the I/O circuitry.
