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US Patent 10692874 3-dimensional NOR string arrays in segmented stacks
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Patent
Date Filed
June 12, 2018
Date of Patent
June 23, 2020
Patent Application Number
16006573
Patent Citations
US Patent 10074667 Semiconductor memory device
Patent Citations Received
US Patent 12105650 Quasi-volatile system-level memory
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US Patent 11508445 Capacitive-coupled non-volatile thin-film transistor strings in three dimensional arrays
US Patent 11507301 Memory module implementing memory centric architecture
US Patent 12068286 Device with embedded high-bandwidth, high-capacity memory using wafer bonding
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US Patent 12073082 High capacity memory circuit with low effective latency
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US Patent 11488676 Implementing logic function and generating analog signals using NOR memory strings
US Patent 11561911 Channel controller for shared memory access
US Patent 11675500 High capacity memory circuit with low effective latency
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US Patent 11705496 Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional NOR memory string array
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US Patent 11710729 Wafer bonding in fabrication of 3-dimensional NOR memory circuits
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Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10692874
Patent Primary Examiner
Thanhha S. Pham
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