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US Patent 10715307 Embedded time of day receiver for clock transmission

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US Patent 12113884 Method and apparatus for adapting, at a sink node, a constant bit rate client signal into the path layer of a telecom signal
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US Patent 12021960 Maintaining a virtual time of day
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US Patent 11934696 Machine learning assisted quality of service (QoS) for solid state drives
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US Patent 11876607 FSYNC mismatch tracking
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US Patent 11863299 Shared communication channel that interleaves 1 PPS signals and messaging
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US Patent 11843393 Method and apparatus for decoding with trapped-block management
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US Patent 11777703 Phase transport with frequency translation without a PLL
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US Patent 11671238 Secondary phase compensation assist for PLL IO delay
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=107153070
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Infobox
Is a
Patent
Patent
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
107153070
Date of Patent
July 14, 2020
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Patent Application Number
165633990
Date Filed
September 6, 2019
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=107153070
Patent Citations Received
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US Patent 10917097 Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits
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US Patent 10972084 Circuit and methods for transferring a phase value between circuits clocked by non-synchronous clock signals
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US Patent 11061432 Data handoff between two clock domains sharing a fundamental beat
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US Patent 11290250 Phase transport with frequency translation without a PLL
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US Patent 11296806 Shared communication channel that interleaves 1 PPS signals and messaging
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US Patent 11323123 Circuit to correct phase interpolator rollover integral non-linearity errors
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US Patent 11424902 System and method for synchronizing nodes in a network device
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US Patent 11496234 Synchronizing update of time of day counters using time stamp exchange over a control plane
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US Patent 11502764 FSYNC mismatch tracking
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US Patent 11502812 Data protocol over clock line
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US Patent 11514994 Method and apparatus for outlier management
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US Patent 11544349 Method for combining analog neural net with FPGA routing in a monolithic integrated circuit
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Patent Primary Examiner
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Eva Y Puente
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Patent Citations Received
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US Patent 11514994 Method and apparatus for outlier management
0
Edits on 16 Nov, 2022
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edited on 16 Nov, 2022
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Patent Citations Received
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US Patent 11502812 Data protocol over clock line
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