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US Patent 10741456 Vertically stacked nanosheet CMOS transistor
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Patent
Date Filed
October 10, 2018
Date of Patent
August 11, 2020
Patent Application Number
16156391
Patent Citations
US Patent 10263100 Buffer regions for blocking unwanted diffusion in nanosheet transistors
Patent Citations Received
US Patent 11894378 Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance
0
US Patent 11837604 Forming stacked nanosheet semiconductor devices with optimal crystalline orientations around devices
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US Patent 11842919 Method of making 3D isolation
0
US Patent 11843001 Devices including stacked nanosheet transistors
0
US Patent 11362091 Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10741456
Patent Primary Examiner
Grant S Withers
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