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US Patent 10762259 Circuit design/layout assistance based on sensitivities to parasitics
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Current Assignee
Diakopto
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Date Filed
June 2, 2019
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Date of Patent
September 1, 2020
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Patent Applicant
Diakopto
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Patent Application Number
16429007
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Patent Citations Received
US Patent 11599698 IR drop analysis based on sensitivity analysis and visualization
US Patent 11347913 Method of reconstruction of post-layout design for graphical display
US Patent 11354483 Parasitic representation of large scale IC packages and boards
US Patent 11544433 Virtual repeater insertion
US Patent 11314916 Capacitance extraction
Patent Jurisdiction
United States Patent and Trademark Office
0
Patent Number
10762259
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Patent Primary Examiner
Suchin Parihar
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