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US Patent 10810484 Hardware accelerator for compressed GRU on FPGA

Patent 10810484 was granted and assigned to Xilinx on October, 2020 by the United States Patent and Trademark Office.

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US Patent 12079658 Detection of invalid machine-specific data types during data conversion
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https://pdfpiw.uspto.gov/.piw?Docid=1081048400
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US Patent 11675592 Instruction to query for model-dependent information
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US Patent 11669331 Neural network processing assist instruction
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US Patent 11604970 Micro-processor circuit and method of performing neural network operation
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Infobox
Is a
Patent
Patent
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Current Assignee
Xilinx
Xilinx
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
108104840
Date of Patent
October 20, 2020
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Patent Application Number
153907440
Date Filed
December 27, 2016
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=108104840
Patent Citations Received
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US Patent 11269632 Data conversion to/from selected data type with implied rounding mode
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US Patent 11361217 Chip and chip-based data processing method
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Patent Primary Examiner
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Eric Nilsson
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=10810484
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Patent citations received
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US Patent 11361217 Chip and chip-based data processing method
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US Patent 11269632 Data conversion to/from selected data type with implied rounding mode
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 US Patent 10810484 Hardware accelerator for compressed GRU on FPGA

Infobox
Is a
Patent
Patent
Current assignee
Xilinx
Xilinx
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10810484
Date of patent
October 20, 2020
Patent application number
15390744
Date Filed
December 27, 2016
Patent primary examiner
‌
Eric Nilsson

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