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US Patent 10818324 Memory array decoding and interconnects

Patent 10818324 was granted and assigned to Micron Technology on October, 2020 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Micron Technology
Micron Technology
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Date Filed
December 18, 2018
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Date of Patent
October 27, 2020
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Patent Applicant
Micron Technology
Micron Technology
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Patent Application Number
16223632
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Patent Citations Received
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US Patent 12133385 Bottom select gate contacts for center staircase structures in three-dimensional memory devices
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US Patent 11894103 Decoding architecture for word line tiles
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US Patent 11974441 Memory array including epitaxial source lines and bit lines
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US Patent 11475947 Decoding architecture for memory tiles
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US Patent 11587606 Decoding architecture for memory devices
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US Patent 11804264 Decoding architecture for memory tiles
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US Patent 11869577 Decoding architecture for memory devices
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10818324
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Patent Primary Examiner
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Douglas King
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