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US Patent 10825526 Non-volatile memory with reduced data cache buffer

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Patent Citations Received
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US Patent 12009049 Non-volatile memory with shared data transfer latches
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US Patent 11915769 Non-volatile memory with isolation latch shared between data latch groups
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US Patent 11705177 Semiconductor memory devices and methods of manufacturing thereof
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=108255260
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US Patent 11651800 Sense amplifier mapping and control scheme for non-volatile memory
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Infobox
Is a
Patent
Patent
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
108255260
Date of Patent
November 3, 2020
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Patent Application Number
164500420
Date Filed
June 24, 2019
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=108255260
Patent Citations
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US Patent 10262704 Apparatuses and methods for providing multiphase clock signals
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US Patent 10373697 Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors
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US Patent 10466903 System and method for dynamic and adaptive interrupt coalescing
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US Patent 10467146 Tape drive with intelligent selection of wrap / track for temporarily storing flushed data
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US Patent 10521118 Methods, systems, and computer readable media for write classification and aggregation using host memory buffer (HMB)
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Patent Citations Received
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US Patent 11386961 Centralized fixed rate serializer and deserializer for bad column management in non-volatile memory
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Patent Primary Examiner
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Michael T. Tran
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Website URL
https://pdfpiw.uspto.gov/.piw?Docid=10825526
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 US Patent 10825526 Non-volatile memory with reduced data cache buffer

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10825526
Date of patent
November 3, 2020
Patent application number
16450042
Date Filed
June 24, 2019
Patent citations
‌
US Patent 10262704 Apparatuses and methods for providing multiphase clock signals
‌
US Patent 10373697 Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors
‌
US Patent 10466903 System and method for dynamic and adaptive interrupt coalescing
‌
US Patent 10467146 Tape drive with intelligent selection of wrap / track for temporarily storing flushed data
‌
US Patent 10521118 Methods, systems, and computer readable media for write classification and aggregation using host memory buffer (HMB)
Patent primary examiner
‌
Michael T. Tran

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