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US Patent 10853448 Hiding latency of multiplier-accumulator using partial results
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Patent
Date Filed
September 11, 2017
Date of Patent
December 1, 2020
Patent Applicant
Habana Labs Ltd
Patent Application Number
15700213
Patent Citations
US Patent 10685082 Sparse matrix multiplication using a single field programmable gate array module
US Patent 10387122 Residue number matrix multiplier
Patent Citations Received
US Patent 12124943 Broadcasting mode of planar engine for neural processor
0
US Patent 11630991 Broadcasting mode of planar engine for neural processor
0
US Patent 11669587 Synthetic scaling applied to shared neural networks
0
US Patent 11328037 Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers
US Patent 10990397 Apparatuses, methods, and systems for transpose instructions of a matrix operations accelerator
US Patent 11016732 Approximate nonlinear digital data conversion for small size multiply-accumulate in artificial intelligence
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10853448
Patent Primary Examiner
Matthew D Sandifer
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