US Patent 10892335 Device isolation by fixed charge

Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.