US Patent 10902098 Logic encryption for integrated circuit protection

A method for encrypting logic includes generating, by a computing system, locking logic for inclusion in a logic circuit. The locking logic is generated based at least in part on an error rate and an attack complexity. The method also includes inserting, by the computing system, a one-way function into the locking logic. The method further includes applying, by the computing system, obfuscation logic to the logic circuit, where the obfuscation logic is applied on top of the locking logic.