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US Patent 10916297 Memory device comprising an electrically floating body transistor

Patent 10916297 was granted and assigned to Zeno Semiconductor on February, 2021 by the United States Patent and Trademark Office.

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Is a

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Patent attributes

Patent Applicant

Zeno Semiconductor

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Current Assignee

Zeno Semiconductor

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Patent Jurisdiction

United States Patent and Trademark Office

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Patent Number

Patent Inventor Names

Yuniarto Widjaja0

Jin-Woo Han0

Date of Patent

February 9, 2021

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Patent Application Number

166931560

Date Filed

November 22, 2019

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Patent Citations

US Patent 10074653 Asymmetric semiconductor memory device having electrically floating body transistor

US Patent 10079236 Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor

US Patent 10103148 NAND string utilizing floating body memory cell

US Patent 10008266 Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating

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US Patent 10026479 Content addressable memory device having electrically floating body transistor

US Patent 10032514 Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating

US Patent 10032776 Method of maintaining the state of semiconductor memory having electrically floating body transistor

US Patent 10056387 Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

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Patent Citations Received

US Patent 11943937 Memory cell and memory array select transistor

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US Patent 12094526 Memory device comprising electrically floating body transistor

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US Patent 11328765 Memory device comprising an electrically floating body transistor

US Patent 11769549 Memory device comprising an electrically floating body transistor

US Patent 11769832 Memory device comprising an electrically floating body transistor and methods of using

US Patent 11882684 Memory device comprising an electrically floating body transistor

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US Patent 11908899 MOSFET and memory cell having improved drain current through back bias application

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Patent Primary Examiner

Allison Bernstein

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Patent abstract

A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

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