Patent attributes
A semiconductor package includes a supporting member that has a cavity and includes a wiring structure connecting first and second surfaces opposing each other. A connection member is on the second surface of the supporting member and includes a first redistribution layer connected to the wiring structure. A semiconductor chip is on the connection member in the cavity and has connection pads connected to the first redistribution layer. An encapsulant encapsulates the semiconductor chip disposed in the cavity and covers the first surface of the supporting member. A second redistribution layer includes wiring patterns embedded in the encapsulant and has exposed surfaces and connection vias that penetrate through the encapsulant to connect the wiring structure and the wiring patterns to each other.
