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US Patent 10929142 Making precise operand-store-compare predictions to avoid false dependencies

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Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
109291420
Patent Inventor Names
James Raymond Cuffney0
Yair Fried0
Jonathan Hsieh0
Adam Collura0
Anthony Saporito0
Edward Malley0
Eyal Naor0
Gregory William Alexander0
...
Date of Patent
February 23, 2021
0
Patent Application Number
163587910
Date Filed
March 20, 2019
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Patent Citations
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US Patent 10417002 Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
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US Patent 10579387 Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor
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US Patent 10013257 Register comparison for operand store compare (OSC) prediction
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US Patent 10067762 Apparatuses, methods, and systems for memory disambiguation
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US Patent 10073789 Method for load instruction speculation past older store instructions
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US Patent 10152327 Apparatus for gating a load operation based on entries of a prediction table
Patent Citations Received
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US Patent 11687337 Processor overriding of a false load-hit-store detection
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Patent Primary Examiner
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Steven G Snyder
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Patent abstract

Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.

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