Patent attributes
Provided are a non-volatile memory device and an operating method thereof. The non-volatile memory device includes a memory cell array having a vertically stacked structure, a bit line for applying a programming voltage to the memory cell array, and a control logic. The memory cell array includes memory cells that each include a corresponding portion of a semiconductor layer and a corresponding portion of a resistance layer. The memory cells include a non-selected memory cell, a compensation memory cell, and a selected memory cell. The control logic is configured to apply an adjusted program voltage to the selected memory cell, based on applying a first voltage to the compensation memory cell, a second voltage to the selected memory cell, and a third voltage to the non-selected memory cell. The adjusted program voltage may be dropped compared to the programming voltage due to the compensation memory cell.
