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US Patent 10943049 Rule check violation prediction systems and methods
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Patent
Date Filed
May 1, 2019
Date of Patent
March 9, 2021
Patent Application Number
16400664
Patent Citations
US Patent 10706201 Circuit design routing using multi-panel track assignment
US Patent 10628546 Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendations
US Patent 10810346 Static voltage drop (SIR) violation prediction systems and methods
US Patent 10089433 Method for triple-patterning friendly placement
US Patent 10331842 Methods and apparatus for automated design of semiconductor photonic devices
Patent Citations Received
US Patent 12067339 Voxel-based electromagnetic-aware integrated circuit routing
0
US Patent 11675960 Machine learning based layout nudging for design rule compliance
0
Patent Jurisdiction
United States Patent and Trademark Office
Patent Number
10943049
Patent Primary Examiner
Helen Rossoshek
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