US Patent 10944012 Area-efficient inverter using stacked vertical transistors
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Patent abstract
An inverter that includes an n-type field effect transistor (nFET) and a p-type field effect transistor (pFET) vertically stacked one atop the other and containing a buried metal semiconductor alloy strap that connects a drain region of the nFET to a drain region of the pFET is provided. Also, provided is a cross-coupled inverter pair with nFETs and pFETs stacked vertically.
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Patent Number
109440120
Date of Patent
March 9, 2021
0Patent Application Number
162382630
Date Filed
January 2, 2019
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US Patent 10944012 Area-efficient inverter using stacked vertical transistors
Infobox
Is a
Patent jurisdiction
Patent number
10944012
Date of patent
March 9, 2021
Patent application number
16238263
Date Filed
January 2, 2019
Patent primary examiner
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